(1) Field of the Invention
The present invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of fabricating deep trench DRAM devices in the fabrication of integrated circuits.
(2) Description of the Prior Art
In the fabrication of integrated circuit devices, deep trench (DT)-based dynamic random access memory (DRAM) devices require certain integration practices. It has been customary to separate the contact etches in the array area from the contact etches in the periphery. Different fill materials (polysilicon in the contact area and tungsten silicide in the periphery, for example) and different contact methods (diffusion contact in the array area and implant contact in the periphery) are reasons for the separation. However, in DRAM devices with a design rule of less than 150 nm, a low resistivity material is required for a contact, especially for those using a deep trench as a storage node. Thus, polysilicon is no longer an attractive option for the contact in the array area because of its high resistivity.
It has also been customary to combine the contact to junctions of support (CS) etch with the contact to gate (CG) etch because of their close proximity in the support (or periphery) area. For example, a self-aligned contact (SAC) process has been used for the bit line contact (CB) etch in the array area while the contact to substrate and the gate contact etch in the array area have been etched together with a moderate selectivity ( less than 3:1) etch method. The moderate etch selectivity recipe has been chosen partly because it must etch through a nitride capping layer on top of the gate. However, this moderate etching selectivity, especially of oxide to nitride, puts the future manufacturing process in jeopardy due to insufficient overlay control between the gate and the contact to the substrate (CS) in the periphery. Overlay control becomes more difficult as the ground rule (or critical dimension of the gate) shrinks especially for those devices having a ground rule of less than 0.17 xc3xa6m. The protection becomes even weaker with insufficient selectivity. A proximity of the contact to substrate (especially an NMOS contact) to the gate contact is a dangerous event. Deleterious effects such as shorting of the gate contact to the metal line, threshold voltage roll-off (lowering of the threshold voltage as gate length decreases), junction leakage, and lowering of the effective saturation current can result. This is especially true for implanted junctions.
A number of patents have addressed aspects of DRAM fabrication. U.S. Pat. No. 5,292,677 to Dennison discloses a single etch stop layer for all contacts wherein all contacts are opened together. U.S. Pat. No. 5,718,800 to Juengling teaches selective contact etching using two masks. U.S. Pat. No. 6,136,643 to Jeng et al etches contact openings using nitride/oxide selectivity. U.S. Pat. No. 6,008,104 to Schrems shows a DRAM process with several selective etches. Self-aligned contact etches are taught, for example, in U.S. Pat. Nos. 6,133,153 to Marquez et al and 5,965,035 to Hung et al. U.S. Pat. No. 4,912,065 to Mizuno et al shows a plasma doping process.
Accordingly, it is a primary object of the present invention to provide an effective and very manufacturable method of DRAM formation in the fabrication of integrated circuits.
It is a further object of the invention to provide an improved etch sequence for DRAM device fabrication.
Another object of the invention is to provide an improved integration scheme of plasma doping in the fabrication of a DRAM integrated circuit device.
Yet another object of the invention is to provide an improved etch sequence and an improved integration scheme of plasma doping in the fabrication of a DRAM integrated circuit device.
In accordance with the objects of the invention, an improved etch sequence and an improved integration scheme of plasma doping in the fabrication of a DRAM integrated circuit device are achieved. Semiconductor device structures are provided in and on a substrate wherein the substrate is divided into an array area and a periphery area. The semiconductor device structures are covered with a dielectric layer. The dielectric layer is concurrently etched through in the array area to form bit line contact openings and in the periphery area to form substrate contact openings. Doped regions are formed in the substrate exposed within the bit line contact openings and the substrate contact openings using a plasma doping process with a separate blocking mask, respectively. Next, the dielectric layer is etched through to form a gate contact opening. Thereafter, the bit line contact openings, the substrate contact openings, and the gate contact opening are filled with a conducting layer to complete forming contacts in the fabrication of a DRAM integrated circuit.